(1) Field of the Invention
The invention relates to the fabrication of integrated circuit devices, and more particularly, to a method of reducing the size of contacts using a retardation layer in the fabrication of integrated circuit devices.
(2) Description of the Prior Art
In the fabrication of integrated circuit devices, feature size has been decreasing. As the design rule decreases, the size of contact holes also decreases. Additionally, the aspect ratio of contact holes has become higher. Contact holes typically pass through multiple conductor layer regions, such as word line and bit line regions, as well as their intervening insulation regions. The increased aspect ratio makes it difficult to fabricate contact holes using conventional lithography techniques without misaligning the holes with respect to the existing device structure. Several techniques, such as tapered contacts and self-aligned contacts, have been proposed for future applications. However, the multi-level contact was found to be much more difficult and complicated than single level contacts even with the tapered or self-aligned contact technologies.
FIG. 1 illustrates such a tapered contact technique. Semiconductor device structures such as gate electrodes 18 have been formed on the surface of the semiconductor substrate 10. Conductors 30 and 40 have been formed on various levels overlying the gate electrodes. Multiple insulating layers comprising borophosphosilicate glass (BPSG), phosphosilicate glass (PSG), silicon oxide, or the like, 60 are formed over and under the conductors. A photoresist mask 80 is formed over the top surface of the insulating layers. The opening A in the photoresist mask is larger than the opening B at the bottom of the contact opening 90. This is a tapered contact opening. However, because of the many layers through which the contact opening is to be made, it is very difficult to avoid the conductors 30 and 40 within the layers. A line short may occur at 95 where a conductor is exposed or very nearly exposed. When the contact opening 90 is filled with a conducting material, a short will occur at 95, leading to device failure.
U.S. Pat. No. 5,663,092 to Lee teaches forming a silicon nitride cap on the top and sidewalls of the conductors. The cap etches more slowly than the insulating layers thus preventing the exposure of the conductors in etching a contact opening. U.S. Pat. No. 5,444,021 to Chung et al teaches exposing and etching away a portion of the topmost conductors, forming oxide spacers on the sidewalls of the conductors to narrow the opening, and then continuing the contact hole etch. U.S. Pat. Nos. 5,389,560 to Park, U.S. Pat. No. 5,492,850 to Ryou, and U.S. Pat. No. 5,482,886 to Park et al all teach methods of partially etching a contact opening, then forming sidewall spacers of polysilicon or oxide to narrow the opening, and then continuing the contact opening etch. U.S. Pat. No. 5,620,917 to Yoon shows a method of making contact openings and capacitors.
Accordingly, it is a principal object of the invention to provide an effective and very manufacturable method of forming a contact opening in the fabrication of integrated circuit devices.
Another object of this invention is to provide a method for formation of a contact opening through a multiple layer structure.
Yet another object of the invention is to form a contact opening having a high aspect ratio.
Yet another object is to widen the process window and relax control on photolithographic alignment and critical dimension in forming a contact opening through multiple layers.
A still further object of the invention is to widen the process window and relax control on photolithographic alignment and critical dimension in forming a contact opening through multiple layers by forming a retardation layer between two adjacent dielectric layers.
In accordance with these objects of this invention, a new method of forming a contact opening through multiple layers by forming a retardation layer between two adjacent dielectric layers is achieved. Semiconductor device structures are provided in and on a semiconductor substrate. A first dielectric layer is deposited over the semiconductor device structures. A patterned conductor layer is formed overlying the first dielectric layer. A second dielectric layer is deposited overlying the patterned conductor layer. A retardation layer is deposited overlying the second dielectric layer wherein the retardation layer has a first etch rate. A third dielectric layer is deposited overlying the retardation layer wherein the third dielectric layer has a second etch rate higher than the first etch rate. A mask is formed over the third dielectric layer having an opening of a first size above one of the semiconductor device structures to be electrically contacted. A contact opening is etched through the first, second, and third dielectric layers and the retardation layer not covered by the mask to the semiconductor device structures to be electrically contacted wherein the contact opening through the third dielectric layer is of the first size and wherein the retardation layer is etched at an angle because of the first etch rate slower than the second etch rate and wherein the contact opening through the second and first dielectric layers underlying the angled retardation layer has a second size smaller than the first size thereby completing the formation of a contact opening in the fabrication of an integrated circuit device.
Also, in accordance with the objects of the invention, an integrated circuit device is described. Semiconductor device structures lie in and on a semiconductor substrate. A first dielectric layer overlies the semiconductor device structures. A first patterned conductor layer overlies the first dielectric layer. A second dielectric layer overlies the first patterned conductor layer. A retardation layer overlies the second dielectric layer. A third dielectric layer overlies the retardation layer. A second conductor layer lies within a contact opening through the first, second, and third dielectric layers and the retardation layer wherein the second conducting layer electrically contacts one of the semiconductor device structures wherein the contact opening through the third dielectric layer is of a first size and wherein the retardation layer has been etched at an angle and wherein the contact opening through the second and first dielectric layers underlying the angled retardation layer has a second size smaller than the first size completing the integrated circuit device.